1. Field of the Invention
This invention relates to electronic systems, and more particularly, to electronic systems which are with advantage implemented in compound semiconductor technology, such as gallium arsenide technology.
2. Description of the Prior Art
The advantage of the high speed of operation of a circuit implemented in compound semiconductor technology (for example gallium arsenide technology), as compared to silicon technology, is well known. In the continuing effort to increase operating speed of integrated circuits and the systems incorporating them, various approaches have been tried in such technology with relatively limited levels of success and/or serious limitations on usability.
Heretofore, the main thrust has been to attempt to provide circuits implemented in gallium arsenide which are to be operatively coupled with other circuits implemented in that technology. That is, there has until now been no serious effort toward providing circuits implemented in "fast" gallium arsenide technology which can be operatively coupled with "slow" silicon-based integrated circuits, such as TTL, CMOS (including advanced CMOS technology), NMOS, Schottky and low powered Schottky (including advanced Schottky technology), all of which will be referred to as "standard logic" herein.
In the event that gallium arsenide-based integrated circuits could be coupled with such standard logic circuits, this would enable one to gain speed in a system based on standard logic by replacing a standard logic silicon-based part with a gallium arsenide based part. In doing so, appropriate input buffer circuits and output buffer circuits, implemented in gallium arsenide technology and coupled in the same package with gallium arsenide based internal logic and/or memory, would be of great advantage. Such input and output buffer circuits would allow one to use standard device packaging, standard testing procedures and equipment, standard input/output levels from and to the standard logic devices operatively connected with the gallium arsenide based integrated circuit, and standard power supplies.
Typical prior art approaches to input buffers for implementation in gallium arsenide technology using MESFETS are shown in FIGS. 1 and 2. However, both such prior art circuits include numerous disadvantages.
For example, referring to FIG. 1, two separate external power supplies are needed (V.sub.cc, positive, and V.sub.ss, negative). These supplies must sink significant current if the buffer is to attain reasonably high speed. Because of this, it is very difficult to use an on-chip charge pump to generate a negative supply for such a chip that has a significant number of inputs, without a large waste in die area and power. This results in a distinct disadvantage for a customer using standard logic since a negative supply must be externally added to the system.
Both the circuits of FIGS. 1 and 2 use a source follower input device (transistors 20, 20a) whose drain is tied to the positive voltage supply V.sub.cc (for example +5 volts). Because of this, the gate to drain diode of transistor 20 or 20a clamps the input to a diode drop level above the voltage level V.sub.cc and an input signal that was raised more than a diode drop level above the V.sub.cc level would begin sinking large currents into he voltage source V.sub.cc. Standard logic families do not exhibit this characteristic and a system that does exhibit this characteristic could well be perceived as undesirable. Furthermore, the transistor 20 or 20a could well be damaged if excessive current were passed through its gate, which could well happen in a realistic system application under a variety of conditions. The net result could be chip failure, perhaps in the field, which results in a tremendous disadvantage to both the chip user and the system user, due to the cost of locating and repairing the failure as well as loss of credibility concerning device reliability.
The approach of FIG. 1 further compounds the problems recited in the preceding paragraph, due to the input path to ground created by the transistor 20's gate-source diode, the diodes 22, 24, 26, and transistor 28's gate-source diode. This condition is in general less desirable than that described in the preceding paragraph since five diodes above ground (approximately 4 volts)is in general lower than one diode above voltage source V.sub.cc (approximately 5.8 volts). This makes the reliability problems mentioned above more likely to occur in any general system and leads to problems when the input signal is expected to interface with CMOS style outputs which attempt to pull up to voltage level V.sub.cc.
The approach of FIG. 2 results in an input signal threshold which is strongly dependent on negative power supply voltage V.sub.ss. As a result, V.sub.ss must be tightly regulated to avoid input signal threshold variations. Since most traditional implementations of standard logic do not have input signal thresholds strongly dependent on any supply voltage, this could be perceived as a significant disadvantage to a user.
The input signal clamping effects of the two prior art circuits make it difficult to offer high ESD specifications for these input signals since they tend to draw high current at low voltage. It is difficult to create a protection device for the input signal that will turn on before the path from input terminal to V.sub.cc or ground turns on and does damage under a static discharge condition.
These input signal clamping effects also make it difficult or impossible to use high voltage logic on the device pins. Since the use of high voltage logic requires that input signals be capable of being raised to levels well above supply voltage V.sub.cc and ground (approximately 10-12 volts above ground) to access special test features or even customer used features, such clamping effects prevent the prior art circuits from being used in these sorts of applications.
In regard to an output buffer circuit for use in the environment described and implementable with advantage in gallium arsenide technology, a general discussion first follows.
Output buffer circuits which may be used to implement three-state functionality are well known in the prior art. The symbol for an active low three-state buffer is shown in FIG. 3. Referring thereto, active low three-state buffer 30 receives a low enable input signal E at enable-disable terminal 32, and a data input signal J at input terminal 34. In response to the data and enable signals, buffer 30 provides an output signal Z at output terminal 36. When the active low three-state output buffer is disabled by application of a high enable signal E (i.e. logical 1), the output terminal 36 is in a high impedance state, and is effectively disconnected from both ground and positive voltage supply V.sub.cc connected to buffer 30. Conversely, when 8 buffer 30 is enabled by a low enable signal E (i.e. logical 0), the output signal Z at terminal 36 is determined by the data input signal J applied to the terminal 34. Thus, with buffer 30 enabled, and a logical 0 data input signal J applied to buffer 30, buffer 30 will provide a logical 0 output signal Z. Conversely, with buffer 30 enabled and a logical 1 input signal J applied to buffer 30, buffer 30 will provide a logical 1 output signal Z.
The active high three-state output buffer operates in a similar manner, except that it is enabled by a high enable signal E, and disabled by a low enable signal E.
Various prior art approaches for implementing CMOS/TTL compatible output buffer circuits are shown in FIGS. 4-6. While each of these circuits is capable of implementation in gallium arsenide technology, no means are provided in any of these approaches to generate a standard three-state condition, as described above. As the advantages of three-state devices are well known, his is a severe disadvantage.
Furthermore, each of these approaches requires two separate external power supplies in addition to ground, one supplying a positive voltage and another supplying a negative voltage. As pointed out above, the inclusion of such a negative supply voltage is a distinct disadvantage for a user of standard logic. In addition, in these approaches, similar to the description of prior art input buffers, a significant current must be sourced into the negative supply in order to achieve high speed. This precludes the use of an on-chip charge pump to generate the negative supply internally without a large waste of power and die area.
In regard to the circuits shown in FIGS. 4 and 5, these circuits use depletion mode pullup devices connected directly to the output. The output lead sinks current to the positive voltage supply if the output signal is pulled up slightly above the level of the voltage supply. This is not characteristic of standard logic devices.
As the circuits of FIGS. 4 and 5 use depletion mode pullup devices, these devices must have current through them while the output signal is in the low state. Since these devices must be large if the output signal i to meet the standard logic output current specifications, such current in the low state will be large and will result in an unacceptable waste of power.
In addition, in the prior art circuits of FIGS. 4 and 6, these circuits require input signal levels which are below ground, further aggravating the problem mentioned above in regard to additional negative voltage supply.
In regard to the prior art logic gate/buffer circuits of FIGS. 7-11, each of these circuits includes significant drawbacks in design and functioning thereof.
In the circuit shown in FIG. 7 two voltage supplies are required, with significant current flowing into the second supply V.sub.ss. Furthermore, such a circuit requires high power for high speed operation.
In regard to the circuit of FIG. 8, such a circuit overcomes the problem of the need for two power supplies, but this circuit has a very poor noise margin, low fan out capability, and is very intolerant of processing, supply voltage, and temperature variations.
Regarding the circuit of FIG. 9, such circuit has a higher fan out capability than the circuit of FIG. 8, but also has a very poor noise margin and is also very intolerant of variations in processing, supply voltage, and temperature.
The circuit of FIG. 10 again has the disadvantage of requiring two voltage supplies, and further involves large signal swings due to the use of depletion mode devices. Furthermore, the capacitor of that circuit must be large enough to drive the on-chip capacitive load, which results in a larger die area than desired.
As shown in the FIG. 11, this circuit requires only a single voltage supply, but has the problem that the output pullup device never quite turns off, and the output pulldown device is a depletion device which comes out of saturation sooner than desired and reduces current available to pull the output signal low, and furthermore conducts more current than desired when the output signal is high for a given low current. SUMMARY
In accordance with the teachings of this invention, the present logic circuit has an input signal lead for receiving an input signal, an output signal lead for providing an output signal, a first voltage supply terminal, and a second voltage supply terminal. The logic circuit includes first, second and third transistors. The first transistor has a first current handling terminal, a control terminal, and a second current handling terminal. Load means are connected between the first voltage supply terminal and the first current handling terminal of the first transistor. The second transistor has a first current handling terminal connected to the first voltage supply terminal, a control terminal connected to the first current handling terminal of the first transistor, and a second currently handling terminal. The third transistor has a first currently handling terminal connected to the second current handling terminal of the second transistor, a control terminal, and a second current handling terminal. The control terminals of the first and third transistors are connected to the input signal lead, and the output signal lead is connected to the first current handling terminal of the third transistor. A load device is connected between the respective second current handling terminals of the first and third transistors and the second voltage supply terminal.